I don't know if this will run at speed yet, but I'm just thinking out
loud. The idea here is for another stage of logic to do some
interpretation before passing commands along:
Refresh is an independent signal.
Commands to the controller are split into 1-hot encoding.
Row miss is pre-computed.
Here's something I'm not sure I like, but it's how I've done it:
Rather than encoding the entry address as a number, I've just slapped
in the 1-hot encoding. That means the entry points are somewhat
redundant and sparse. They actually take up 1/4 of the 512 program
words.
Also, I haven't thought it all through. I'm not sure that refresh
will work the way I want it to if I do it this way.
Anyhow, I just thought I'd let you see the essential feedback loop
between instructions and instruction address and how commands are
mixed in.
/*
Memory controller state machine
This is the lower end of the memory controller, being the basic state machine.
The following needs to be translated by other logic to make this work:
- Convert commands to 1-hot
- Arbitrate refreshes
- Detect row misses
There are some hypothetical inefficiencies in this design. For instance,
if a row is already closed from some other operation (like a refresh),
the row miss logic won't know to skip the precharge and go directly to
activate. Either we'll fix this or determine it to be so rare that we
don't care.
The following are the 1-hot command bits:
0 - read
1 - read with row miss
2 - write
3 - write with row miss
4 - refresh
5 - precharge all
6 - lmr
Reset is 1's on all command bits.
*/
module mem_ctl_cpu (
pci_clock,
mem_clock,
reset,
busy,
cmd_in
);
input pci_clock, mem_clock, reset;
output busy;
input [6:0] cmd_in;
reg [8:0] ins_addr;
wire [31:0] ins;
RAMB16_S36_S36 mprg_ram (
.DOA(ins), .DOPA(),
.DOB(), .DOPB(),
.ADDRA(ins_addr), .CLKA(mem_clock),
.DIA(32'b0), .DIPA(4'b0),
.DIB(reg_write_data), .DIPB(4'b0),
.ADDRB(reg_write_addr[8:0]), .CLKB(pci_clock),
.ENA(1'b1), .SSRA(1'b0),
.ENB(1'b1), .SSRB(1'b0),
.WEA(1'b0), .WEB(reg_write && !reg_write_addr[9]));
// Split out instruction fields
wire [8:0] next_addr;
wire [5:0] allow; // same bits as cmd_1hot_in (missing lmr+noop)
assign {allow, next_addr} = ins;
wire [6:0] select = cmd_in & {1'b1, allow};
assign ins_addr = select ? select : next_addr;
endmodule
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