I have been working on trying to get the video controller simulation to
run a compiled program. Unfortunately I know almost zero Verilog and
have been hitting some snags.
I added this to the RAMB16_S36_36.v file:
initial begin
$readmemb("/login/mcnamara/svn/ogp/drivers/lib/video_controller/32x32.bin",
mem, 0);
end
Based on digging around on the web, this should pre-initialize the RAM
block defined by "reg [35:0] mem [0:511];" with the contents on the
specified file. However when the simulation runs, the video controller
never loads the first instruction.
So, now for some questions. I dawned on me a moment ago that the RAM
block is 36 bits wide. Does the $readmemb command just read a bit
stream in and break it up as necessary to place it in the defined
memory? Am I going to have to update the compiler code to generate 36
bit words?
Actually, the more important question is, did I do the correct thing to
initialize the memory and in the right spot (it's right below the "reg
... mem" line)? If so, I would expect the simulation to at least load
the first instruction, though it may be an incorrect instruction.
Thanks for the help and sorry to interrupt your memory controller work.
BTW if it would help to send you the 32x32.bin file, I can.
One last question. Does the video controller expect little endian or big?
Patrick M
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