Here is a current state of the memory controller. Some details remain. It seems to send the right signals to the memory, but it should be tested against a simulator for the memory chip.
It was quite tricky to get the busy signal registered early enough. I
resorted to making it logic expression, hoping that it is not too
complex to fulfil the timing contraits. The good thing is that the most
complex stage (4) does not depend on 'busy'. (In other words I fled
the Eval Two-Level State Machine instead of fighting it.)
The controller supports read and write of 1 data per cycle random access
for a continuous stream of in-row addresses. On the other hand, a cycle
is wasted here and there in other places for simplicity.
It is worth noting that timing-configuration takes significant die
space. It can be disabled with FIXED_TIMING, which is probably just as
well for FPGA use.
Loose bits:
* The memory clock, data strobing and sampling stuff is not properly
implemented. Need expertise here.
* There is curretly only a "test ROM" module for the programmable
bits. Replace with proper RAM modules.
Is it okay to commit the current work to Subversion? I can use
rtl/mem_ctl/pnp (pipelined non-programmable) or the like, in case
there'll be more implementations.
mem_ctl-0.1.tar.bz2
Description: BZip2 compressed data
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