There are PLL's in the XP10 and in the TV Encoder.
The PLL's in the XP10 can take there input clock
from any of the source clocks on the board one way or
another (13.5MHz or 14.318MHz). The code is not
written yet, but it should be possible to have a set
of programmable dividers in the forward and feedback paths
of the PLL's to generate almost any frequency.
The TV Encoder chip can generate a reference clock from
the 13.5 MHz crystal given by :
FCLK = 13.5MHz * {PLL_INT[5:0] + (PLL_FRACT[15:0]/216)}/6
where PLL_INT and PLL_FRACT are registers inside the
TV Encoder. There is a trace that connects the TV Encoder
to the Lattice XP10 FPGA and there are links between the
XP10 and Xilinx FPGA.
The 14.318MHz oscillator connects to the XP10 FPGA
direct. This clock can go the PLLs inside the this FPGA
or be passed to the Xilinx FPGA via the links mentioned
previously.
I'd draw a diagram, but there are just too many configurations
possible to cover.
Howard.
On 8/3/06, Timothy Miller <[EMAIL PROTECTED]> wrote:
On 8/3/06, Koen De Vleeschauwer <[EMAIL PROTECTED]> wrote:
> Correct me if I'm wrong, but I only see three possibilities:
> - using an external PLL. I see no external PLL in the schematic, however.
> - using a PLL in another chip on the board, eg. the Conexant. CLKO of the
Conexant seems unconnected, however.
> - or reloading the FPGA with a different bitstream whenever the modeline
dotclock changes.
>
> Which do you use?
I think we might be using a PLL inside of the XP10.
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