On 8/20/06, Diego Sáenz <[EMAIL PROTECTED]> wrote:
About this DMAs usually have a pair of registers(address, count) that you can read or write and between this and the bus the counters that generate addresses for the transfer and stop transfer when zero. In the comodore amiga you can program audio(and others i think) DMAs so that when the count end it reload counters from registers and generate an interrupt. So you do: - Get a pair of buffers - Fill the buffers - Program DMA with one buffer - Start the transfer - Program DMA with other buffer without stop transfer in progress(simply wrote address and count without touching control reg) - Wait for the interrupt When you get the interrupt you known that the DMA is transfering the second buffer and the first is transfered and empty so you: - Reuse the empty buffer - Program DMA with not in use buffer whitout stop transfer in progress In this way you do not get idle sound(in amiga case) and the procesor do the minimum work possible. Can this be applied here? Is it used by someone? sorry i am one amiga fan :P
This is quite typical double-buffering. The only problem I haven't totally resolved yet (in any case) is that while DMA is going on, you really don't want to try to do a PIO to the same device. This isn't a logical problem so much as a physical one. During the transfer of a DMA burst, the bus is tied up doing something, and it's going to be doing it for a while. Any attempt by the CPU to access the bus is going to suffer a massive latency. Imagine how many CPU cycles are wasted while waiting for 32 PCI bus cycles at 33MHz. I'm pondering sensible alternatives that generally avoid using interrupts and have the driver and GPU communicate via flags in a DMA buffer, which the GPU accesses on its own schedule. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
