On 8/25/06, Jon Smirl <[EMAIL PROTECTED]> wrote:
Part of the VRAM is always mapped by the CPU. This is how software fallbacks are implemented.
Every software rendering routine needs to be wrapped by code that knows how to reposition the aperture offset.
When in command stream mode the PIO registers are rarely used by the CPU. This is because the internal GPU command stream can also write to the same registers. GPU operations are controlled by writing to these registers. For example bilblt. I'm simplifying but there is really only one command type in a command stream. The command just consists of a bunch of register addresses and the values to write to them. There is no bitblt command, just this generic command that can write to the registers that control the bilblt engine. You can totally control the chip this way, even change the video mode.
This isn't how I've seen it done. Besides, If you don't have a bitblt command, then your packet has to include register addresses. If you do have a bitblt command, the addresses are implicit, making the packet smaller. As a fallback, I would provide a command that could do arbitrary register writes, but it would be seldom used.
You can do every command externally by turning off the command stream and writing the registers via PIO. That is a good way to test the chip. This model is why Radeons have 2,000 registers.
That's how we'll get it up and running on the earliest drivers. Throwing in DMA too soon adds too many variables and too many things to break. We discourage direct PIO writes to the register set, but they can be done. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
