Timothy Miller wrote:
On 8/27/06, Jack Carroll <[EMAIL PROTECTED]> wrote:
The DDC injection box sounds like a very interesting solution to
one class of configuration and test problems. It's probably a
useful test tool in its own right, for checking out the system's
behavior with DDC codes. Am I right in thinking that it's not a
general solution to configuring all possible arbitrary modes
directly from timing specs or modeline-style data?
I think EDID is able to specify detailed timing numbers. What would
be missing?
http://www.vesa.org/Public/EEDIDguideV1.pdf
http://en.wikipedia.org/wiki/EDID
It appears to have all the ability of an X modeline:
54-71: Descriptor Block 1
54-55: Pixel Clock (in 10 kHz) or 0
If Pixel Clock is non null:
56: Horizontal Active (in pixels)
57: Horizontal Blanking (in pixels)
58: Horizontal Active high (4 upper bits)
Horizontal Blanking high (4 lower bits)
59: Vertical Active (in pixels)
60: Vertical Blanking (in vertical pixels/lines)
61: high significant bits for Vertical Active (4 upper bits)
high significant bits for Vertical Blanking (4 lower bits)
62: Horizontal Sync Offset (in pixels)
63: Horizontal Sync Pulse Width (in pixels)
64: Vertical Sync Offset (in lines) (4 upper bits)
Vertical Sync Pulse Width (in lines) (4 lower bits)
65: high significant bits for Horizontal Sync Offset (bit 7-6)
high significant bits for Horizontal Sync Pulse Width (bit 5-4)
high significant bits for Vertical Sync Offset (bit 3-2)
high significant bits for Vertical Sync Pulse Width (bit 1-0)
66: Horizontal Image Size (in mm)
67: Vertical Image Size (in mm)
68: high significant bits for Horizontal Image Size (4 upper bits)
high significant bits for Vertical Image Size (4 lower bits)
69: Horizontal Border
70: Vertical Border
71: Interlaced or not (bit 7)
? (bit 6)
Stereo or not (bit 5)
Separate Sync or not (bit 4-3)
Horizontal Sync positive or not (bit 2)
Vertical Sync positive or not (bit 1)
? (bit 0)
And it has sync:
20: VIDEO INPUT DEFINITION
bit 7: 0=analog, 1=digital
if bit 7 is digital:
bit 0: 1=DFP 1.x compatible
if bit 7 is analog:
bit 6-5: video level
00=0.7, 0.3, 01=0.714, 0.286, 10=1, .4 11=0.7, 0
bit 4: blank-to-black setup
bit 3: separate syncs
bit 2: composite sync
bit 1: sync on green
bit 0: serration vsync
Forgot that you also need to change the video level for sync on green.
So, that is the format to use since it is a VESA standard. I presume
that we can find room for a 256 byte EEPROM. Don't know what the second
128 bytes are going to be used for so perhaps we don't need them.
I still think that we should have some basic method on the board for
starting mode (default video mode):
480i @ 30
480p @ 60
VGA 640x480 @ ??
Setting in EEPROM
and a write enable for the EEPROM.
Note, IIUC, 480p and VGA are slightly different in the non-visible part
of the signal.
Do we also need Vertical frequency for VGA? (60, 70, 72) since some
monitors won't do 60? And, 50 which would change to PAL 50 formats.
This would permit the user to set the board up using a borrowed VGA or
his TV (with our CD of monitor information).
--
JRT
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