Timothy Miller wrote:
On 9/6/06, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
Typo this should be 643.
It would be more useful if they had a model that supported DDR/DDR2
SDRAM. I realize that 133 MHz SDR DRAM is a bit slow for the RAM
access and it appears that it would only support 50 MHz system bus
access which would be an issue since it would have to use the DRAM
interface for fast system bus access and that means intermediate
logic if we use a stock chip.
It would be ideal if we could trick the DSP into thinking TRV11 (or
whatever model number) was its memory.
It appears that that would work.
The DSP would have to have more of a local bus than a memory bus so
that we could insert wait states.
They have different memory blocks that can be configured individually
for memory specs. However the 133 MHz interface is synchronous. It
does have bus arbitration including a bus request signal. It appears
that when our chip dropped the bus hold that it would need to give up
memory access while the DSP was accessing the video memory until it got
the bus back (bus hold acknowledge was received).
Another option would be to give the DSP a small local memory and have
TRV11 force-feed streams in and out.
IIUC, local memory to do the conversion would allow the conversion to
proceed in parallel with other actions. Since the TI chips have 64 DMA
channels, it seems that it would be a good idea to make use of them if
possible.
--
JRT
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