On 9/12/06, ABC XYZ <[EMAIL PROTECTED]> wrote:
I am trying to learn by reading the stuff Timothy and others on the list write.I checked the new code to figure out how Timothy was able to "speed up" this code. Some of the changes I understand (like the binary -> one-hot encoding). Then there are parts like this that I cant figure out by myself: // DQS (strobe signals) // Insert timing diagram here reg [4:0] dqs_en0; reg dqs_en1; // synthesis attribute equivalent_register_removal of dqs_en0 is "no" // synthesis attribute equivalent_register_removal of dqs_en1 is "no" always @(posedge clock) dqs_en0 <= {5{expect_write}}; always @(negedge clock) dqs_en1 <= expect_write || dqs_en0[4]; ddrff4 dqs_ff (.Q(dqs_out), .C0(~clock), .C1(clock), .D0(dqs_en0[3:0]), .D1(4'b0), .OE(dqs_en1)); Could anyone explain to me why this is better than the original code? Is the 5 x register put there to improve fan-out or something??
IIRC, the primary modification here was to replicate dqs_en0 so that there is one per output signal. There is a synthesizer option to force registers into IO buffers (iobs). But this doesn't always have the results I want. The synthesizer was making a single register for dqs_en0 for all four outputs, and the routing to the iobs, with a fanout of 4 wasn't meeting timing. What I did was manually replicate the register so that there was one per iob (and would then the registers in the iobs would get used rather than one in random logic). Seeing that I had four functionally identical registers, the synthesizer wanted to rip them out. I put in the metacomment (synthesis attribute) to force all four of the regs to be retained. I would have achieved the same result if I had forced the max fanout from dqs_en0 to be 1. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
