int factorial(int i) {
if(i == 0)
return 1;
return i*factorial(i-1);
}
Can this be done in Verilog?
Of course, it's generally wise to convert recursive algorithms in C to explicitly iterative ones to avoid stack overflow, but sometimes it's just easiest to express things factorially. Can that be done in Verilog? I suppose you'd have to create some stack (ring buffer?) to store your previous data and always use that?
The reason I ask is because I'm working on a pixel-perfect cubic bezier curve rederer, and once it's done in C I'd like to try doing it in Verilog, but I have no idea how to express my recursive algorithm in hardware. TrueType fonts use bezier curves, so I figured it would be cool to have the ability to accelerate them in hardware :)
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