> Later, we should consider figuring out how to do USB 1.1. The "Full > Speed" 12 megabit data rate won't be a problem on the I/O's, but the > protocol will surely be a challenge to implement. Also, with really > clever logic, we MIGHT be able to do the 480MHz for USB 2.0, although > I don't think we'll really need it. The approach to examining > recorded bus activity should be to download on demand, rather than try > to download the whole buffer at once.
There seems to be a number of small Physical Layer IC's available which implement the USB Transceiver Macrocell Interface (UTMI). For example: SMSC: Small Footprint Hi-Speed USB 2.0 Device PHY with UTMI Interface http://www.smsc.com/main/catalog/usb3290.html Cypress Semiconductor: MoBL-USB(TM) TX2 USB 2.0 UTMI Transceiver http://www.cypress.com/portal/server.pt?space=CommunityPage&control=SetCommunity&CommunityID=209&PageID=259&fid=285&rpn=CY7C68000A&ref=pfm I was thinking it should be possible to come up with a small adapter that uses one of these IC's. The adapter could then be soldered on to one of the Sil178 pads. So we'd also need an implementation of UTMI/SIE (from opencores?) and application endpoints in the FPGA, and client application using libusb to communicate with the card. Robert _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
