On Sun, 07 Jan 2007 14:32:23 -0500, Timothy Miller wrote: On Sun, 07 Jan 2007 14:32:23 -0500, Timothy Miller wrote:
> I'm still working on simulating the PCI target, and I have a master I've > written as part of that test. The master will go on to be rewritten to > be the master that we put into OGD1, so I'm making sure it works > properly as well. > > I encountered a situation where the master violated bus protocol. One > of the things I'm testing is situations where either the master or > target inserts wait states. For those of you interested in the > protocol, I can go into detail, but the nutshell is that I was > simulating a "slow" bus master. That is, the master was inserting wait > state cycles. This corner case is a little hard to fully test, but I > think I have come up with an appropriate solution, and it appears to > work for reads. Contriving a case for writes may be difficult. Have you considered (and I know this is a pain in the ass but still it might be less of a pain in the ass :) than hunting bugs) using a protocol state analyser? I have had a look at spin[1] before, but I think that is more for protocol design testing rather than protocol implementation testing. Are there any packages out there that do PCI protocol implementation testing? Matt [1] "The Spin Verification System" http://dimacs.rutgers.edu/Volumes/Vol32.html _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
