On 2/17/07, Simon <[EMAIL PROTECTED]> wrote:
On 2/17/07, Timothy Normand Miller <[EMAIL PROTECTED]> wrote:
> On 2/17/07, Dieter <[EMAIL PROTECTED]> wrote:
> > OGC will have an even slower bus.
>
> Depends on how many PCIe channels we design into it. There will be at
> least one (about as fast as PCI-32 66MHz).
What's the tradeoff for putting more lanes in?
Design complexity, design schedule, testing, expense.... all of the bad things.
IIUC, PCIe gets superlinearly more complex as you add lanes, having to
do with the logic required to reinterleave the data.
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Favorite book: The Design of Everyday Things, Donald A. Norman, ISBN
0-465-06710-7
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