On 2007-03-18, Nicolas Boulay wrote: > >> * Only basic one-cycle operations goes in the CPU. If we need any > >> multi-cycle operation (div?), we could add it as IO ports, using > >> the "modularised RISC" idea, > >> http://lists.duskglow.com/open-graphics/2006-April/005307.html. > > > >Oh, yeah! Good idea. > > > > Be carefull of all the lost cycle to read/write data to the good > memory register. 3 (or 4, one more to execute the instruction) access > for a div at least + the div it-self. You can't also assume that a > memory access will be one cycle latency because the memory adress > decoder for such register could be hudge and slow.
If we were to add div, I assume we'd massively serialise to save gates. So, maybe 16 cycles? The CPU will do other things while waiting for the result, so in effect the CPU only spends 3 cycles on it. If we use an operation frequently with tight dependencies, then this is not feasible. The address decode, that's a 9-10 bits comparison, so 4 gate-levels, or do I leave out something? _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
