On 4/16/07, Paul Brook <[EMAIL PROTECTED]> wrote:
> Perhaps it would be even simpler to have two interrupts. One as you
> describe -- a sync interrupt -- which could not be turned off, A second
> for a service request which would be triggered by firmware on the board
> or the DMA controller.
>
> Then the issue of turning the sync interrupt off and on is moved to the
> driver since the APIC Intel acronym == Advanced Programmable Interrupt
> Controller) on the motherboard already has the hardware to turn off
> (ignore) an interrupt.
On a typical PCI system each device only gets a single interrupt pin (a PCI
bus has 4, but each device is only supposed to use 1), and several devices
share an interrupt line.
Thus all interrupts should be maskable on the device, and probably combined
into a single output after masking.
What we did on TROZ was have the following sorts of controls for
interrupts (inspired by what we'd seen with other chips):
- Specify the condition under which an interrupt would be triggered
- Enable the condition to occur
- Enable a triggered interrupt to assert the interrupt line on the bus
- Reset the interrupt condition state
For video, the they are, respectively:
- The bit in the VC instruction that specifies when the interrupt happens
- The config register that lets us pay attention to that bit, setting
a flag when it happens.
- A configuration flag that gates the interrupt signal onto the PCI bus
- A register to write to that clears the flag
Oh, and course, you need a register to read that tells you which of
potentially multiple interrupt conditions are being asserted.
This isn't overkill. There's a difference between the triggering
event, the flag that gets set as a result of the triggering event, and
the signal to the host that causes a CPU interrupt. There are
situations where you'd want the event to happen and be noted (by
setting the flag) without it interrupting the CPU.
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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