-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Timothy Miller wrote: > Ok, here's what we're going to do. We've been able to save some > money on the design of the board and manage to get most dotclocks > we'd want to get. The board has two crystal oscillators on it. > One is at 150MHz. The other is at 155.52MHz. Each one goes into > an adjustable 8-bit counter divider that lets you divide by any > number from 1 to 256 (although some of the smaller numbers will > result in clock rates that are too high), then the output of that > goes into a clock manager that multiplies it by 32 (adjustable in > design but fixed for use). The same logic is duplicated for each > head, so each has its own independent clock at any of the available > frequences. > > The formula for the dot clock is: > > freq = 150*32/N or 155.52*32/N > > The actual clock frequency is 1/4 or 1/2 of this, because we > process multiple pixels in parallel.
I'm slightly confused about this; is the "freq" result in the formula above the physical clock that's clocking the logic, or is it the pixel clock? The description of how "freq" is generated indicates that it's the physical logic clock. In which case, if multiple pixels are processed in parallel, isn't the logical pixel clock 4x or 2x this, not 1/4 or 1/2 this? My immediate question: Doesn't the 8-bit counter introduce a huge amount of jitter into the clock signal? Can the Xilinx DCM actually clean up jitter? I'm not that familiar with the low-level capabilities of DCMs in this regard. Thanks for any information. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.2 (MingW32) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFGZ4zwhk3bo0lNTrURAtAgAKCHr/vKsLWggZ0VkC1ASbW6EgAtiACgqA7u AY/MzEQR2F/ACkGCiLSnAaE= =Kr6d -----END PGP SIGNATURE----- _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
