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(I'm assuming it was an accident your last reply didn't go to the list,
so forgive me if it was meant to be a private reply!)

howard parkin wrote:
> For analogue and Dual link DVI, freq is the pixel clock.
> For Single link DVI, freq needs to be 2 x the pixel clock rate.

OK. Out of curiosity, how come analogue and single-link DVI aren't the
same, and dual-link DVI a different case (since analog and single-link
DVI have pretty much the same max pixel clock)

Perhaps this is just a facet of how the external video encoders take
their data; single/double wide/edge etc.?

>> Is this scheme based on the DCM configurations mentioned here:
>> 
>> http://www.xilinx.com/products/boards/s3estarter/files/s3esk_frequency_generator.pdf
>> 
>> http://www.xilinx.com/products/boards/s3estarter/files/s3esk_frequency_generator.zip
> 
> This is where I first heard of the DCM tweeks, but we are not using
> the frequency synthesis scheme described in these papers. In the
> Xilinx scheme, there was significant jitter in the input clock because
> they used a non-integer division of the source clock, and hence the
> period between +ve edges of the DCM input clock varied ie jitter.
> We always divide our source clock by an integer, so that the
> period between successive clock cycles is always the same, ie
> no jitter.

Is the clock generator RTL available anywhere - will it be part of the
GPL part of the RTL?

I'm curious mainly because I've been playing around with VGA output from
a Spartan3 starter kit module, and so far, I've pretty much been limited
to [EMAIL PROTECTED], due to generating the pixel clock using a simple DCM
configuration driven by the 50MHz crystal. Having this kind of
flexibility would be great!

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