On 8/12/07, Michael Meeuwisse <[EMAIL PROTECTED]> wrote: > I assume the synthesis is automagically using the schematic on page 6 > of this document; > http://www.xilinx.com/bvdocs/appnotes/xapp467.pdf
Yes, I think it is. The synthesizer automatically inferred it from using the * operator, but I did poke around in there a bit, and it does appear to be doing something reasonably sane. > Is there no way to do the first step (the multipliers) as extra logic > in stage 2? No wait, that was running at clock_2x, so maybe stage 1? > The final add of all intermediate results in stage 4? What I was thinking of doing is pipelining the multiplier across the ALU and MEMIO stages. The multiplier would never be used in address computation anyhow. So, yeah, basically the multiplies get done in the ALU stage and the adds in the MEMIO stage. > > I got no idea how much the delay is through the dedicated hardware > multiplier. Try clipping x and y to 17 bits and see what the > synthesis results are then. Are they (besides unusable) fast enough > then? I've seen it manage to do 8x8 multiplies (prop delay for the higher bits is longer) in under 8ns. I would bet we could keep the 16x16 parts to under 10ns. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
