On 8/14/07, Michael Meeuwisse <[EMAIL PROTECTED]> wrote: > I'm actually using Apple Mail. Switched to plain text, hopefully that > solves it.
Perfect. Thank you! > Ok. I just thought that verilog was indentation-sensitive and only > x_lookup_r and y_lookup_r where running at 2x clock. The "Compute x, > y and v" part seemed like direct wiring unrelated to any clock at > all. Anyway, not all of stage 2 is running at 2x clock is it? The > reason I did this was because it looked like the logic to get x_o and > y_o didn't seem like much. The lookups are being CLOCKED in the 2x domain. Writes are happening coincident with the falling edge of 1x, while reads are happening coincident with the rising edge of 1x. (This way, we can simulated a 3-port RAM with only 2 ports.) But the synthesizer knows that both clocks are from the same clock generator and can therefore ensure that things crossing between them meet timing (or report when they don't). So you can think of y_o and x_o as being in 1x, because that's where they're headed. (That is, the delay from the lookup registers is allowed to be as much as one full clock period in 1x, minus clock skew due to different loadings on the two clock trees.) So the logic to get y_o and x_o isn't much, but that's not the point. What I'm saying is that you don't want to put the multiplier between the register file and the lookup registers, because as it is, the lookup registers are built right into the same slices as the memory. > > No. I know VHDL too, and it doesn't instantiate physical registers > > unless you your behavioral code is triggered by a clock edge. The > > syntax is a little different from Verilog, but it's the same idea. > > I blaim that then. I don't see why the wire x_o etc assignments > aren't in such a 'always' block. You can do this: always @(posedge clock) x <= y; Where x is recomputed whenever there's a rising edge of the clock. (sequential) Or you can do this: always @(y or a or b) x = y; Where x is recomputed whenever any of the items in the sensitivity list (y, a, b) change. (combinatorial) Doing this: assign some_wire = y; Is the same as the second type of always block, except that the sensitivity list is implicit in whatever is in the expression. I don't tend to use combinatorial always blocks a great deal. Just probably how I approach things. I think that usually, assigning to wires (continuous assignment) is easier to read, especially for simple expressions. If this were a full-custom design, BTW, x_o and y_o would indeed be in always blocks, triggered on a clock edge. This is because it would be preferable to register the outputs, and the full-custom design would give us the freedom to do that AND have efficient logic. > > I understand what you're going for here, but I'm unable to keep them > apart in verilog. I don't see which parts are before the register, > and which parts are after. It's all a bunch of assigments to me. > The "posedge clock" is the key. In simulation, that is the trigger for what causes the behavioral code in the always block to execute. In hardware, that resolves to registers. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
