Timothy Normand Miller wrote:
We're hoping to get the GPU to exceed 100MHz in the FPGA. Maybe we
Here, you're referring to the Spartan, right? And the DMA controller
(aka nanocontroller?) is separately constrained by the PCI bandwidth?
If you're targeting 66MHz 32-bit PCI (or equivalent) and the
nanocontroller can do one 32-bit read or write per cycle, am I right in
understanding that the nanocontroller would then need to run at well
over 133MHz to keep the PCI bandwidth satisfied? I say well over
because there will obviously be other instructions executed besides just
reads and writes (though obviously you don't have to saturate the peak
/theoretical/ bandwidth of the interface...).
BTW, the only reason to do this is because without it, a multiply
would take at least 4 times longer due to the overhead of explicit
shifts and branches. Do we care?
I would imagine Lattice's tools still infer multipliers and I believe
there is a fast(ish) multiplier implementation for the Lattice XP
architecture using LUTs and carry chains (it's alluded to in the datasheet).
Well, it won't be fast in one cycle, and if it's pipelined, it'll be a
lot more logic than we can probably justify.
Right -- see results below.
not sure if Lattice registers have Enable inputs, or they may be
mutually exclusive with async resets.
At a glance, it looks like the asynchronous set/reset and the clock
enable are independent (and there is a clock enable). I'm taking this
from page 6 of http://www.latticesemi.com/documents/DS1001.pdf.
I'm going to try to get a feel for the cost of multipliers on the
Lattice part. They haven't sent me a Synplify license yet, though.
Isn't all that free?
Yes, but it took a while for the license email to arrive.
I'm still getting to know the tools, but it looks like a 32x32->64
multiplier with registers at the inputs and outputs requires 567 slices
(12% of the device) and operates at 45MHz post-PAR on LFXP10C,5 (using
ispLEVER 7 & Synplify 8.8 under wine). This is using the Project
Navigator defaults (Synplify targets 200MHz and achieves 61MHz; PAR
targets 56MHz and achieves 45MHz -- I have no idea where or how those
constraints were specified).
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