Here is my attempt to refine the I/O ports. For PCI I'm making wild
guesses, so nailing down the ports is just an easy way to expose my
misunderstandings. The point is to gain some understanding of how the
nanocontroller will interact with the PCI controller (and memory).
Memory read
in MEM_READREQ_FREE Free slots in command pipe.
out MEM_READREQ_ADDR First address to read.
out MEM_READREQ_COUNT Number of words to read.
in MEM_READREPLY_DATA Data stream from memory.
in MEM_READREPLY_AVAIL Number of words in FIFO.
Memory write
out MEM_WRITE_ADDR Start address.
out MEM_WRITE_COUNT Defauts to 1. (Needed at all?)
in MEM_WRITE_FREE Free slots in output FIFO.
out MEM_WRITE_DATA Data stream to memory.
Master read
in PCI_MASTER_READREQ_FREE Free slots in command pipe.
out PCI_MASTER_READREQ_ADDR Host-mapped address to read.
out PCI_MASTER_READREQ_COUNT Number of words to receive.
in PCI_MASTER_READREPLY_DATA Data stream from host.
in PCI_MASTER_READREPLY_AVAIL Number of words in FIFO.
Master write
out PCI_MASTER_WRITE_ADDR Host-mapped address to write.
out PCI_MASTER_WRITE_COUNT Number of words to send.
in PCI_MASTER_WRITE_FREE Free words in output FIFO.
out PCI_MASTER_WRITE_DATA Data stream to host.
Target of write (we're reading)
in PCI_TARGET_WRITEREQ_ADDR Target address of write.
in PCI_TARGET_WRITEREQ_COUNT Number of words to receive.
in PCI_TARGET_WRITEREPLY_AVAIL Number of words in FIFO.
out PCI_TARGET_WRITEREPLY_DATA Data stream from host.
Target of read (we're writing)
in PCI_TARGET_READ_ADDR The requested address.
in PCI_TARGET_READ_COUNT The requested number of words.
in PCI_TARGET_READ_FREE Free words in output FIFO.
out PCI_TARGET_READ_DATA Data stream to host.
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