Thank you very much for your reply. Actually, I was asking this because I'm designing (open) hardware that will use a DDR SODIMM module. So I think I will design the PCB so that parallel resistors can be easily added, and will try to avoid them if possible ; as you said they waste a lot of power. From what you said, I should get away without them (I will only run the memory chips at about 100MHz) but given the cost of prototype 4-layer PCBs with BGA packages I do want to avoid a board respin.
Sebastien On Tuesday 16 October 2007 14:50:26 howard parkin wrote: > Strictly these resistors should be present. However, under > certain conditions, Its possible to get away with not > putting them on. > > On OGD1, we can only run the memories at DDR400 (200MHz) > due to FPGA speed limitations. For SDRAM these days, that's pretty > slow. Also, we only have to deal with point-to-point links on > the data lines. Under these conditions, series termination at > the source ends of the memory data lines is OK. There is > an application note on the Micron site somewhere that details this approach > and gives some test results. To cut down reflections, we use series > resistors at the DRAM end to match the 50-ohm-or-so trace impedance > and we control the driver impedance at the FPGA end by drive strength > selection. > > Doing series termination is a big plus, because it cuts down > the power. Parallel termination would have probably required > a fan on the FPGA and heatsinks on the memories. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
