Sebastien Bourdeauducq wrote:
On Tuesday 16 October 2007 13:57:54 Ing. Daniel Rozsnyó wrote:
Sebastien Bourdeauducq wrote:
Hi,

I've had a look at the board schematics from Transversal Technology, and
I wonder why termination resistors that connect the DDRAM signal lines to
a 1.25V (Vtt) supply are not present. From what can be read in various
sources, DDRAM uses SSTL-2 signaling which requires that resistor (see
http://download.micron.com/pdf/presentations/dram/plat7justin.pdf p.8 for
instance).
The presentation is about multiple DDR DIMM's, not single chips.

That's the same, DIMM DDR memory modules contain only the chips plus the series resistor in the 20-30 ohm range, and a serial EEPROM to store information about the chips used. See an example schematics at www.elixir-memory.com/products/file/Elixir_ DDR_512MB_B%20Die_TSOP_SODIMM_R1.0%20-%20160806.pdf p.5 ; and a quick visual inspection of a memory module from a PC shows the same.

Not exactly the same - motherboards (and your initial link to a presentation) contain multiple slots for DIMM modules. That setup includes connectors and signal integrity could/will be a problem.


Is that because the PCB traces are short enough that you can get rid of
that resistor and still get good signal integrity ?
I think this is because point-to-point links.

What do you call a "point to point" link ?
See the SSTL-2 spec at http://download.micron.com/pdf/misc/sstl_2spec.pdf.
There is nothing about that "point to point" thing.

P2P for me is a `direct chip to chip trace without branching`, in this case also for 1 driver and 1 receiver per line (not counting address lines now - they are a mystery even after reading the above pdfs, that the termination is same for load of 2 (data) and 16 (addr) when using 2 modules with 8 chips..).


And the chips already contain some termination circuitry.

Are you sure about this point ? I've always read the opposite

Well, that is valid only for DDR2 (http://en.wikipedia.org/wiki/DDR2_SDRAM : "..DDR2's bus frequency is boosted by electrical interface improvements, on-die termination .. "). Not sure if they talk about the CLK pair only or all the signals.


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