On 06/11/2007, Timothy Normand Miller <[EMAIL PROTECTED]> wrote: snip we make models > of 74-series in Verilog. We could start at that level. Which chips > are used here? I don't remember many of the 74-series chips, but > others do and can look at the diagrams. Let's just start posting the > snippets of Verilog code to the list for each of the chips and build > up from there.
For those wondering, the 74138 has three inputs, 3 chip enables. 8 Outputs. Depending upon the inputs and gates, only ONE output may go low. Here is a datasheet with a truth table (a table explaining when what works) *http://www.ee.latrobe.edu.au/internal/workshop/store/pdf/74LS138.pdf -see pg 2 another with the package symbols *http://focus.ti.com/lit/ds/symlink/sn74ls138.pdf Perhaps now Lourens has cleaned up the pages about our tools, we could add this as an example to show how to write a verilog file, take it through to writing a test, and even viewing it on the simulator. I have written up a truth table on the wiki - http://wiki.opengraphics.org/tiki-index.php?page=Development_Tools (we probably need to eventually move it from this page) I have been reading that some users new to linux feel confused with the multitude of ways of getting started - it is how i felt. We might consider recommending only one editor to new ones. Advanced used will always have their own editor they use and love but for someone coming from Windows, they need to be able to start somewhere. One that will work.. will do for getting them started, until they feel comfortable with branching out. hmm. It is only probably because of the maturity of the list that I dare ask this question<g>. What editor would we recommend? We want to be able to show -line by line- how to set it up so it handles most if not all they need. I have run out of time for now, someone want to add the verilog to the page? We may want to later go and explain what we are doing, but put the verilog in first. and we can get to it then. > <snip> > module IC74138( > input en1, > input en2, > input nen3, > input [7:0] in, > input [2:0] select, > output out); > > out = in[select] & en1 & en1 & ~nen3; > > endmodule > > > module IC74377( > input e_bar, > input [7:0] in, > output reg [7:0] out, > input clock); > > always @(posedge clock) begin > if (e_bar == 0) out <= in; > end > > endmodule > <snip> > -- jb _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
