On 11/11/2007, [EMAIL PROTECTED] <[EMAIL PROTECTED]> wrote: > > Great description of all the ways the design was > less than optimal... I am sure that all the various > ways Verilog would produce less than optimal synthesis > for that block will come up again, and I thank you > for taking to the time to explain the problems so we > can improve. > > nick
Perhaps you might add a page, maybe after the verilog tutorials which is for code reviews and comments like these. jb _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
