Sorry I didn't attach the multiplier last night but the Tb that was
created by hand. Here is the rtl code for the float multiplier.

André Pouliot wrote:
> Here is the new version for the floating point multiplier.  The thread
> is from July but I just had the time to rework on it.
>
> This version is basically the same except some amelioration like the
> result is forced to zero when one of the input value is a denormalized
> number or zero. For the case that the value is infinite or NaN the
> result is forced to infinite except if multiplied by zero.
>
> There is also a C++ test bench generator to build a verilog test bench
> with random value and some fix corner case. That generator is based on
> the float25 class in the old OGA model. The generator for now is
> relatively basic and could be ameliorated.
>
> Actually there seem to have a bug somewhere in the code. The bug seem to
> be a rounding problem that cause a variation of "1" in the result of the
> multiplication.  I'm not sure if it's from the C++ code or the verilog
> that is the cause of the bug.
>
> Timothy Normand Miller wrote:
>   
>> Yeah.  Use the new_model code, and define an actual class for float25
>> that limits the precision and also has this new behavior as well.
>>
>> On 7/30/07, Nicolas Boulay <[EMAIL PROTECTED]> wrote:
>>   
>>     
>>> For the float25, is it possible to use the C model to see the beavior
>>> of this inf*zero=zero feature ?
>>>     
>>>       
>
>
>   
> ------------------------------------------------------------------------
>
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// Open Graphics float25 multiplier tb generator
// Written by André Pouliot
//Created : 2007/05/25
//Modified : 2008/02/02


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//module float25 multiplication
module floatmult25 (
clk,
floatA,
floatB,
floatResult
);

//Port definition
input                   clk;
input[24:0]             floatA;
input[24:0]             floatB;
output[24:0]    floatResult;


//internal signal
reg             signStg1;
reg                     ZeroA;
reg             ZeroB;
reg                     InfiniteNanA;
reg             InfiniteNanB;
reg[7:0]        exponentAStg1;
reg[7:0]        exponentBStg1;
reg[15:0]       mantissaAStg1;
reg[15:0]       mantissaBStg1;

reg             signStg2;
reg                     ZeroStg2;
reg                     InfiniteNanStg2;
reg[8:0]        exponentStg2;
reg[33:0]       mantissaStg2;


reg             signStg3;
reg                     ZeroStg3;
reg                     InfiniteNanStg3;
reg[9:0]        exponentStg3;
reg[15:0]       mantissaStg3;

reg             signStg4;
reg[7:0]        exponentStg4;
reg[15:0]       mantissaStg4;

//---------------------
//Begin logic
//---------------------

//First stage evaluation if value is zero/denormalised or infinite/NaN 
//and bit splicing in independant field
always @(posedge clk) 
begin : Stage1
  signStg1 <= floatA[24]^floatB[24];    //sign result evaluation
  exponentAStg1 <= floatA[23:16];               //bits slice
  exponentBStg1 <= floatB[23:16];
  mantissaAStg1 <= floatA[15:0];
  mantissaBStg1 <= floatB[15:0];
  ZeroA <= |floatA[23:16];                              //zero/denormalised
  ZeroB <= |floatB[23:16];
  InfiniteNanA <= &floatA[23:16];               //infinite/NaN
  InfiniteNanB <= &floatB[23:16];               
end

//second stage multiplication and addition of the mantissa and exponent
always @(posedge clk) 
begin : Stage2
  signStg2 <= signStg1;
  exponentStg2 <= exponentAStg1 + exponentBStg1;
  mantissaStg2 <= {1'b1,mantissaAStg1}*{1'b1,mantissaBStg1};
  ZeroStg2 <= ZeroA & ZeroB;
  InfiniteNanStg2 <= InfiniteNanA | InfiniteNanB;
end

//Stage 3 mantissa select for reforming the data for next stage
//and exponent adjust depending on mantissa result.
always @(posedge clk) 
begin : Stage3
  signStg3 <= signStg2;
  ZeroStg3 <= !ZeroStg2;
  InfiniteNanStg3 <= InfiniteNanStg2;
   if (mantissaStg2[33]) begin
    exponentStg3 <= exponentStg2 - 126;
    mantissaStg3 <= mantissaStg2[32:17];
  end else begin
    exponentStg3 <= exponentStg2 - 127;
    mantissaStg3 <= mantissaStg2[31:16];
  end
end

//Stage 4 Rounding to zero or infinite before output.
always @(posedge clk) 
begin : Stage4
  //signStg4 <= signStg3;
  if (exponentStg3[9] || exponentStg3 == 0 || ZeroStg3) begin//if negatif or 
zero round to zero
    exponentStg4 <= 8'h00;
    mantissaStg4 <= 16'h0000;
    signStg4 <= 0;
  end else if(exponentStg3[8] || exponentStg3 == 255 || InfiniteNanStg3) begin
    exponentStg4 <= 8'hFF;
    mantissaStg4 <= 16'h0000;
    signStg4 <= signStg3;
  end else begin
    exponentStg4 <= exponentStg3;
    mantissaStg4 <= mantissaStg3;
    signStg4 <= signStg3;
  end
end

assign floatResult[24] = signStg4;
assign floatResult[23:16] = exponentStg4;
assign floatResult[15:0] = mantissaStg4;

endmodule
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