I added some basic rounding logic in the floating point multiplier
without adding another stage. It still lack in the last stage some logic
to prevent an overflow that the rounding could cause. Even if that even
is unlikely.

A floating point adder as been added to the svn repository. The adder is
a 5 stage adder it include the same basic rounding as the multiplier
without the protection for overflow.

When testing for resources used, every float adder take approximately
400 slices while the multiplier take ~ 40 slices.


Nicolas Boulay wrote:
> 10 slices is nothing compare to the fixed point multiplier in an asic
> design. Maybe this could a design optimisation, the day you need to
> find some free slice, to remove this stage for few unit.
>
> 2008/2/5, André Pouliot <[EMAIL PROTECTED]>:
>   
>> Well it would add a fifth stage to the multiplier.  That added stage
>> would take something like 10 more slice in the design. Not that much but
>> we are already taking 35 slice and 1 multiplier. It's rather small if
>> you consider that we are having like 28K slice and 96 multiplier in the
>> spartan3-4000.
>>
>> The question is still how much space do we need for the full design? If
>> we have the space it's not that long to add that stage later in the
>> design, it would take something like 2 hour with basic simulation of the
>> multiplier for design correctness.
>>
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