[Open-graphics] Open source FPGA flow

[Mark]

This is purely academic, not targeting a real architecture, but still... 
probably a very useful starting point if anybody is seriously 
considering pursuing open source FPGA implementation tools.

        VPR 5.0: Modernized FPGA Architecture, Design and CAD

        Jason Luu, Peter Jamieson, Ian Kuon, Jonathan Rose

The VPR toolset for FPGA architecture and CAD exploration is used
worldwide by many researchers (and some companies, as we found last
FPGA seminar) to enable a wide variety of research relating to FPGAs.
Its architecture flexibility, high quality algorithms and robustness
have made it a standard.

In this seminar we will describe a new (imminent) release of VPR that
adds a number of modern features and capabilities to the toolset:

1. Single-Driver Routing Architecture (that works across a wide range
   of routing architectures).

2. Heterogeneous logic blocks - the ability to describe different hard
   blocks, in addition to the regular soft logic.

3. A wide range of transistor-optimized design files, spanning architecture,
   different area-delay tradeoffs, and IC processes down to 22nm,
   based on the Arizona PTM process models.

4. Robustness.  (That is, trying to maintain VPR's legendary software
   quality).  This release comes with regression tests, that it also
   passes!

In addition we will describe an open source full CAD flow from Verilog
to routing.  It begins with ODIN (for Verilog parsing and
elaboration), passes through a hacked version of Berkeley's ABC logic
synthesis (that permits heterogenous structures to pass through,
unhurt) and then to T-VPACK and VPR.  This full flow is also part of
the release.

We will describe the set of research questions that arose (and remain)
in the development of this new version of VPACK/VPR, and the full
flow.  We will also describe all of the features that were left out
and need to go in future releases.
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