I continued digging a little, the vid_control module has vid_clock as an input, module video_wrapper uses this module and also has vid_clock as an input. Right now, the s3_top_level maps vid0_clock or vid1_clock to these inputs, but these signals are somewhat odd;

BUFG Vid0_BUFG (
    .I(vid0_clock_ext),
    .O(vid0_clock)
    );

vid0_clock_ext is once again, an input:

// Tempory hack to make everything pass synthesis
        input mem_clock_ext,
    input vid0_clock_ext,
    input vid1_clock_ext,

Am I deducting correctly that this comment is an elegant "TODO", and the clocks aren't dynamic yet?

On 4 Mar 2008, at 02:24, Timothy Normand Miller wrote:

The simplest way is to have a high frequency into a divider.  But
that's kinda limited.  Another thing you can do is take the DCM
output, run that through a divider, and then use the output of that as
feedback.

The problem is that the frequencies needed don't really have a common divider, unless you start running several GHz. Say, for example, we want some basic ones;

640x480 @ 60Hz = 25.175 MHz (say 25, works just as fine)
800x600 @ 60Hz = 40 MHz
1024x768 @ 60Hz = 65 MHz

I guess we could do something like, run at 130 MHz. Then we get
640x480 - divide by 5.2 (count to 5, every fifth time count to 6?)
800x600 - divide by 3.25 (count to 3, every fourth time count to 4?)
1024x768 - divide by 2

Correcting the clock like that all the time is bound to give odd display results. So I don't know how to do it, but a divider sounds imho impossible.

I think.  I'm really not sure how Howard did it.

On 3/3/08, Michael Meeuwisse <[EMAIL PROTECTED]> wrote:
Quick question.


Cheers,

Michael
www.projectvga.org

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