On 3/5/08, Michael Meeuwisse <[EMAIL PROTECTED]> wrote: > > On 5 Mar 2008, at 21:16, Timothy Normand Miller wrote: > > > > What you want is the bridge bus clock, because this is a configuration > > register, set through making writes to PCI. I think we may call it > > "bridge_clock" in the S3 top level. > > > I was more thinking that this clock might be 133MHz or 156.25MHz, so > that I should reuse those.
Think about where the config data is coming from. It's coming form the driver, via the PCI bus. And in our case, also the bridge. Since the data is from the bridge clock domain, that's the clock you have to use in order to be able to sample the data correctly. > But if there's already a clock defined I > would just include an extra input pin. However, when looking into how > this would fit in the existing stuff I found out that the vid_control > module is already tracking a bunch of registers and how to set them, > so I just changed that one to contain the new bits. That meant also > changing some other files so I attached a diff. vid_control, > vid_wrapper and s3_top_level are affected. > > Could someone (I think actually Patrick McNamara, you're the > maintainer of most of these files correct?) have a good look at what > I'm doing? Am I handling the outgoing clock signal correctly? > > > Cheers, > > Michael > www.projectvga.org > > > -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
