Michael Meeuwisse wrote: > > On 5 Mar 2008, at 21:16, Timothy Normand Miller wrote: >> >> What you want is the bridge bus clock, because this is a configuration >> register, set through making writes to PCI. I think we may call it >> "bridge_clock" in the S3 top level. > > I was more thinking that this clock might be 133MHz or 156.25MHz, so > that I should reuse those. But if there's already a clock defined I > would just include an extra input pin. However, when looking into how > this would fit in the existing stuff I found out that the vid_control > module is already tracking a bunch of registers and how to set them, > so I just changed that one to contain the new bits. That meant also > changing some other files so I attached a diff. vid_control, > vid_wrapper and s3_top_level are affected. > > Could someone (I think actually Patrick McNamara, you're the > maintainer of most of these files correct?) have a good look at what > I'm doing? Am I handling the outgoing clock signal correctly?
At first glance, things look correct. I'll study it more as I have time, my main system is offline and I'm using my laptop so long simulations take a while. I do have a couple of comments/questions. These are just questions I haven't researched and that came to mind while looking at this patch. 1. How precise does the actual clock frequency need to be? 640x480x60 is specified as 25.175MHz with standard blanking intervals. How close to we have to be? Is 25MHz close enough? That's a 0.7% error. Somebody that know more about the technicalities of monitors and video equipment may be able to answer. 2. At reset divisor0 and divisor1 are set to 0. This is an invalid value for both. What happens to the clock generator with these values? Should we initialize to a good value? The first question I can answer when I get a moment to study the code under simulation. The second is a design question for which I want opinions. If we do initialize it, to what frequency? 3. Does Xilinx have a Verilog DCM simulation model? I haven't made it to their site to check so by the time someone answers this, I may already know. If not, can we write one in pure Verilog? I think the answer is no. If both answers are no, then I will work on a VPI module to emulate the DCM so that we can actually simulate the video controller properly. Patrick M _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
