The arb/mem 1K registers are split such that offsets 0x00 - 0x0f are
the arbiter, and 0x10 - 0x1f are the memory controller.
Reg 0 is the LMR command. The data word is split as follows:
Bits [14:13] are the BANK select (which select which of the mode
registers to load)
Bits [8:0] are the data to load into the register.
Reg 2 is the PRECHARGE command. Any write triggers.
Reg 3 is as follows:
Bits [10:0] are the refresh delay in memory clock cycles.
Bit 11 is the refresh_enable control (active high)
Quoting the source code:
LMR:
To load the mode register, first ensure that refresh is disabled.
Check the spec for the DRAMs for required delays, which must be
enforced by software.
A precharge command must be issued (reg 2).
Then LMR or LMR-extended (reg 0) can be issued.
Now, these are the memory controller regs (offsets from offsets):
0: r2w_wait <= reg_data;
1: w2r_wait <= reg_data;
2: act2rw_wait <= reg_data;
3: r2pre_wait <= reg_data;
4: w2pre_wait <= reg_data;
5: pre2act_wait <= reg_data;
6: act2pre_wait <= reg_data;
7: refresh2act_wait <= reg_data;
8: cas_latency <= reg_data;
The values for those regs are not what you expect them to be. There's
an email I posted ages ago that explained them, but here are the
correct numbers to hard-code:
parameter r2w_wait = 4'b1000; //cas latency = 3
parameter w2r_wait = 4'b1000; //Twtr + 1 = 3
parameter act2rw_wait = 6'b111100; //Trcd - 1 =2
parameter r2pre_wait = 3'b100; //cas latency - 1 = 2
parameter w2pre_wait = 6'b110000; //Twr + 1 = 4
parameter pre2act_wait = 6'b111100; //Trp - 1 = 2
parameter act2pre_wait = 12'b111110000000; // Tras - 1 = 7
parameter refresh2act_wait = 22'b1111111110000000000000; //Trfc - 1 = 13
parameter cas_latency = 5'd6; // cas_latency = cl[4:1] - cl[0] x 0.5
So I guess what we need to do next is figure out what to load into the
mode registers.
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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