On Wed, Aug 20, 2008 at 4:41 AM, Petter Urkedal <[EMAIL PROTECTED]> wrote:
> >> Now (and this is what I think you may be talking about), if you're >> going to turn the cache off and then do caching in HQ, then you have >> to mask the address in software. > > Yes, except that I didn't consider caching in HQ. If we want to cache > the request, could we not just as well enable the hardware cache? Depends on side-effects, but generally yes. >> The pipe being empty doesn't tell you enough. You could have a bunch >> of wait states inserted on the PCI bus, so the queue empties, but the >> transaction isn't finished. At the same time, the null command has to >> be inserted into the pipe so that it synchronizes with everything >> else. > > If the pipe empties during a transaction, poll_pci() would save the > current address and exit. The next time it is called, it will receive > the next write command. It will then issues a new write request to the > bridge and continue where it left off. So, the code can handle each PCI > command individually. The inner write-loop is just an optimisation. Cool. > >> I've looked over the code you wrote, but reading assembly is hard, so >> I'm going to have to come back to it again before I can comment >> intelligently. > > Maybe I better ask that you ignore the code and write a C version when > you get the time. I have the sense that there are many details here > which require knowledge of the overall architecture to get right. I > think I'll be more helpful with the translation, as I know the assembler > and HQ well. No. I need to know this stuff. I just need to concentrate. And we can always use more comments. :) -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
