sravanthi mantha wrote: > Hi Everyone, > I am looking for a sync_generator verilog code, which can produce h_sync, > v_sync and black signals, for a display controller,can someone help me on > this.
Here's my try at the generator (see attachments). The generator in sync.v consists of a pixel clock input, two counters for x and y, and combinational logic for the three outputs vsync, hsync and black. Zero values of the counters correspond to the top left corner of the visible area, so that the counters can be used directly as screen coordinates. There are module parameters for the resolution and for the rest of the timing. The defaults are from http://tinyvga.com/vga-timing One easy to forget thing is the counter size, which depends on the size of the sum of all horizonral resp. vertical values, not on the visible resolution. Does Verilog have a logarithm and an upwards-rounding function? I didn't put in a reset because behavioral simulation and programmable hardware (FPGAs, CPLDs) don't need it, and an ASIC will, in the worst case, start working correctly after the y counter wraps around. Adding a reset should be straighforward, though. The test bench test_sync.v runs the generator for two frames and one line, and writes the output to an image file output.xpm. Besides the timing parameters which are passed to the generator, the test bench has one extra parameter for the pixel frequency (in case it's used with a post- synthesis model). - Viktor Pracht -- Psssst! Schon vom neuen GMX MultiMessenger gehört? Der kann`s mit allen: http://www.gmx.net/de/go/multimessenger
sync.v
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test_sync.v
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