On Tue, Nov 11, 2008 at 6:12 PM, Viktor Pracht <[EMAIL PROTECTED]> wrote:
> I didn't put in a reset because behavioral simulation and programmable
> hardware (FPGAs, CPLDs) don't need it, and an ASIC will, in the worst case,
> start working correctly after the y counter wraps around. Adding a reset
> should be straighforward, though.
Nice work. Now, if you want to target a real chip with that, you're
going to need to be sure to register all of your outputs. If you
don't, then the signals won't change in sync with each other because
their phase relative to the clock will depend on the combinatorial
delay. My recommended change amount to is a pipeline delay between
the counters and the outputs, so it doesn't affect the timing in any
way. Here are the changes:
output reg hsync,
output reg vsync,
output reg black
...
always @(posedge clk) begin
hsync <= (h_res + h_front) <= x && x < (h_res + h_front + h_sync);
vsync <= (v_res + v_front) <= y && y < (v_res + v_front + v_sync);
black <= x >= h_res || y >= v_res;
end
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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