What follows is some of the preprocessing logic for rasterizer
parameters. Each parameter has a start and a delta value. Whenever
either of them changes, we want to pre-align them to simplify the
summing logic, which I posted earlier (an which I'll update soon).
Caveat: The processed parameters are ephemeral. Whenever either of
the original values changes, both of the processed values will change.
Consider the case where you have loaded X1_start and X1_delta and
then you have caused some counting to occur where the delta is added
to the start some number of times. If you were to decide you wanted
to change the delta, the current value of X1_start would get
overwritten by the original value when you first wrote the register.
// Take a start and a delta (32-bit floats), and align them
module raster_sum_prep(
input clock,
input reset_,
input start_sign_in,
input [7:0] start_exp_in,
input [22:0] start_mant_in,
input delta_sign_in,
input [7:0] delta_exp_in,
input [22:0] delta_mant_in,
input param_changed_in, // Either start or delta changed
output reg start_sign_out,
output reg [7:0] exp_out,
output reg [26:0] start_mant_out,
output reg delta_sign_out,
output reg [26:0] delta_mant_out,
output reg param_changed_out,
input busy);
wire advance;
// Stage 1: Denormalize and compare exponents
reg start_sign_a;
reg [7:0] start_exp_a;
reg [23:0] start_mant_a;
reg delta_sign_a;
reg [7:0] delta_exp_a;
reg [23:0] delta_mant_a;
reg [8:0] s_min_d;
reg [8:0] d_min_s;
reg param_changed_a;
always @(posedge clock or negedge reset_) begin
if (!reset_) begin
param_changed_a <= 0;
end else begin
if (advance) param_changed_a <= 0;
if (param_changed_in) param_changed_a <= 1;
end
end
always @(posedge clock) begin
if (advance) begin
// Denormalize
start_sign_a <= start_sign_in;
start_exp_a <= start_exp_in;
start_mant_a[22:0] <= start_mant_in;
start_mant_a[23] <= start_exp_in != 0;
delta_sign_a <= delta_sign_in;
delta_exp_a <= delta_exp_in;
delta_mant_a[22:0] <= delta_mant_in;
delta_mant_a[23] <= delta_exp_in != 0;
// Compare exponents by subtracting them
// negative results will indicate the lesser
s_min_d <= start_exp_in - delta_exp_in;
d_min_s <= delta_exp_in - start_exp_in;
end
end
// Stage 2: Shift
always @(posedge clock or negedge reset_) begin
if (!reset_) begin
param_changed_out <= 0;
end else begin
if (advance) param_changed_out <= 0;
if (param_changed_a) param_changed_out <= 1;
end
end
always @(posedge clock) begin
if (advance) begin
start_sign_out <= start_sign_a;
delta_sign_out <= delta_sign_a;
exp_out <= start_exp_a;
start_mant_out <= {start_mant_a, 3'b0};
delta_mant_out <= {delta_mant_a, 3'b0};
if (d_min_s[8]) begin // start > delta
delta_mant_out <= {delta_mant_a, 3'b0} >> s_min_d[7:0];
end
if (s_min_d[8]) begin // delta > start
exp_out <= delta_exp_a;
start_mant_out <= {start_mant_a, 3'b0} >> d_min_s[7:0];
end
end
end
assign advance = !busy || !param_changed_out;
endmodule
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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