Hi.
Thanks for the offers of help. I've built a couple of FPGA images now
and successfully downloaded them onto the FPGA. I can tell that the
image that I built is running because I added a magic value that is
returned by reading an XP10 register, so this is the first two hurdles done.
The XP10 image was built using the "free" version of ispLever, so I will
try to write up some documentation on how I did that. Is it worth
checking the project files in? I'm not quite sure which files are
needed, but I think it would be possible to put them all in a
sub-directory on there own (so that we don't pollute the directory tree
with different project files for different tools - I'm assuming that
different ispLever versions might want different files?)
I'm assuming that there is no reason that I should have to rebuild the
S3 just because I've changed the XP10? (assuming I don't change the
bridge interface.) I beleive that I should be able to rebuild the
Xilinx images at work - we use a lot a Xilinx FPGAs and I'm sure that we
have tools that will do it. The tools won't be the WebPack though,
everything we use at work runs on real operating systems and is mostly
driven by the command line (just like god intended).
I've got quite a convoluted test set-up now, but it seems to give me all
I want, so I'll describe it a bit.
The victim PC is a ASUS P2B. I got the motherboard off of e-bay for £5
including P&P. I've chosen this motherboard so that I can use coreboot,
instead of the stock BIOS. coreboot is an open source PC BIOS
replacement. The huge win here is that as well as being able to see the
source and modify it, serial port debugging is the first feature they
get working.
So the victim PC is connected to the development PC via a serial cable.
There is also the JTag connection between the two.
coreboot allows you to override the option ROM in a PCI card by adding
an image to the coreboot rom. I've done this, but in a special way.
The image in the coreboot ROM for the OGD1 is a small serial monitor
program that accepts a couple of 1 character commands. This has the
effect than when I boot the victim PC I get a wait prompt when the OGD1
BIOS gets called. From this prompt I can then insert a real OGD1 BIOS
and run that.
The advantage of this setup is that the time from recompiling the BIOS
to actually testing it is less than 20 seconds, and only involves
resetting 1 PC that has no disks attached. There's no FLASH burning,
and no reinserting PCI cards.
It's taken a couple of weeks to get this set up and working properly,
but it's really a joy (previously I had to reboot the victim PC twice
and swap out the PCI cards, and then burn a new option ROM).
It should be possible to get a similar set-up working with the stock
BIOS. The only snag is that the stock BIOS probably hasn't set-up the
superIO at the time the VGA ROM gets called, so the serial port won't
work by default. This would mean that any monitor would be motherboard
specific.
If people fancy trying this then they should try to find a motherbaord
that is supported by coreboot, and preferably one that is supported by
serialice.
Maybe this is a bit off topic?
MM.
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