On Fri, Nov 6, 2009 at 4:52 AM, Mark Marshall <[email protected]> wrote: > Hi. > > Thanks for the offers of help. I've built a couple of FPGA images now and > successfully downloaded them onto the FPGA. I can tell that the image that > I built is running because I added a magic value that is returned by reading > an XP10 register, so this is the first two hurdles done. > > The XP10 image was built using the "free" version of ispLever, so I will try > to write up some documentation on how I did that. Is it worth checking the > project files in? I'm not quite sure which files are needed, but I think it > would be possible to put them all in a sub-directory on there own (so that > we don't pollute the directory tree with different project files for > different tools - I'm assuming that different ispLever versions might want > different files?)
I wouldn't check in the whole project. Xilinx tools have an "archive" function that will zip up just the files that are needed, leaving out anything that can be rebuilt. I don't know if Lattice tools have anything similar. If not, we just need to understand what each of the files are and collect them together. Also, we should not host them in the SVN repo, because the project file would be a non-ascii blob. We can put them on Traversal's web site or something. > I'm assuming that there is no reason that I should have to rebuild the S3 > just because I've changed the XP10? (assuming I don't change the bridge > interface.) I beleive that I should be able to rebuild the Xilinx images > at work - we use a lot a Xilinx FPGAs and I'm sure that we have tools that > will do it. The tools won't be the WebPack though, everything we use at > work runs on real operating systems and is mostly driven by the command line > (just like god intended). That's true. You're probably in good shape with the S3 for now. We still need someone to help maintain it (thank you, Patrick) in the event that we do need to make changes. Also, there's plenty of room to add logic, like basic acceleration, etc. > > I've got quite a convoluted test set-up now, but it seems to give me all I > want, so I'll describe it a bit. > > The victim PC is a ASUS P2B. I got the motherboard off of e-bay for £5 > including P&P. I've chosen this motherboard so that I can use coreboot, > instead of the stock BIOS. coreboot is an open source PC BIOS replacement. > The huge win here is that as well as being able to see the source and > modify it, serial port debugging is the first feature they get working. > > So the victim PC is connected to the development PC via a serial cable. > There is also the JTag connection between the two. > > coreboot allows you to override the option ROM in a PCI card by adding an > image to the coreboot rom. I've done this, but in a special way. The image > in the coreboot ROM for the OGD1 is a small serial monitor program that > accepts a couple of 1 character commands. This has the effect than when I > boot the victim PC I get a wait prompt when the OGD1 BIOS gets called. From > this prompt I can then insert a real OGD1 BIOS and run that. This is very cool. I was worried about you and others not having a sufficient debug environment. It's also good that you can do more extensive debugging on your end so that we can leave it as last resort to ask Howard to use the PCI bus analyzer. > The advantage of this setup is that the time from recompiling the BIOS to > actually testing it is less than 20 seconds, and only involves resetting 1 > PC that has no disks attached. There's no FLASH burning, and no reinserting > PCI cards. > > It's taken a couple of weeks to get this set up and working properly, but > it's really a joy (previously I had to reboot the victim PC twice and swap > out the PCI cards, and then burn a new option ROM). > > It should be possible to get a similar set-up working with the stock BIOS. > The only snag is that the stock BIOS probably hasn't set-up the superIO at > the time the VGA ROM gets called, so the serial port won't work by default. > This would mean that any monitor would be motherboard specific. > > If people fancy trying this then they should try to find a motherbaord that > is supported by coreboot, and preferably one that is supported by serialice. > > Maybe this is a bit off topic? No. It's totally on-topic. People need to be able to do this kind of debugging, whether it's with OGD1 or something else. Documenting your setup so people can duplicate it would be really helpful to everyone. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
