Andre Pouliot: >The schematic for the ALU is finally in electronic format. It took me some time >to go through my note. It should be conceptually correct. I still have to go in >a better depth analyze each stage and the math/logic used but it should give >something rather compact and fast. Some stage may seem extremely big and have a >great logical depth but OGA2 isn't planned for now. The newer FPGA being with >bigger LUT and more resource for the multiplier. > >As you can see in the schematic I splited the ALU and the instruction decoder. >Mostly because with 1 instruction decoder we can control multiple ALU.
I'm not sure if this is already in the SVN, but I did some work some ages ago splitting the floating point functional units into modules, so a lot of the work, at least for some of the ALU stages should already be there. Furthermore, separating the decoder from the ALUs seems like a smart idea. I like it -- Life on the earth might be expensive, but it includes an annual free trip around the sun. Kenneth Østby http://langly.org
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