I thought about writing it in behavioral Verilog. If there were an open source Verilog simulator that used some kind of JIT compilation for performance, then that would be acceptable. Otherwise, interpreted Verilog is just not going to be acceptable in performance for the main simulator.
On Thu, Nov 1, 2012 at 2:29 PM, <[email protected]> wrote: > Le 2012-11-01 19:11, Patrick McNamara a écrit : > > I still like the idea of being able to sleep and wake in the MIDDLE >>> of code (rather than only being able to start at the beginning of a > >>> function), so we should consider adding a feature that can do long_jmp >>> as well. >>> >> ... > > Either that, or I am missing a use case for sleeping in the middle of >> a chunk of simulation code. >> > Either that, or you'all can use VHDL directly that has everything and even > more ;-) > > process... > do_something(); > wait for 10ns; > do_something_else(); > wait; > end process; > > And with VHPI, GHDL can even communicate with external code compiled by > GCC. > > just my two lines, > >> Patrick M >> > Yann > ______________________________**_________________ > Open-graphics mailing list > [email protected] > http://lists.duskglow.com/**mailman/listinfo/open-graphics<http://lists.duskglow.com/mailman/listinfo/open-graphics> > List service provided by Duskglow Consulting, LLC (www.duskglow.com) -- Timothy Normand Miller, PhD Assistant Professor of Computer Science, Binghamton University http://www.cs.binghamton.edu/~millerti/<http://www.cse.ohio-state.edu/~millerti> Open Graphics Project
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