On 2 November 2012 10:56, Timothy Normand Miller <[email protected]> wrote: > I thought about writing it in behavioral Verilog. If there were an open > source Verilog simulator that used some kind of JIT compilation for > performance, then that would be acceptable. Otherwise, interpreted Verilog > is just not going to be acceptable in performance for the main simulator.
resend to the list. On 2 November 2012 13:06, Timothy Normand Miller <[email protected]> wrote: > On Fri, Nov 2, 2012 at 11:34 AM, Eitan Adler <[email protected]> wrote: >> Quick search finds: http://www.veripool.org/wiki/verilator > Anyhow, this is very interesting. The design would have to be synthesizable > completely (which complicates things a lot), and this would affect > portability. -- Eitan Adler _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
