On Wed, Dec 12, 2012 at 03:46:27PM -0500, Timothy Normand Miller wrote: > It wouldn't be TOO hard to get some small FPGA or microcontroller, wire it > to a set of flash chips, and hook that to a PCIe bus. Then we'd want to > use something like NILFS2 as the filesystem to handle wear-leveling in > software. > > We can just expose the raw flash organization to the host so that the host > software can allocate blocks and schedule accesses to individual flash > chips. So we'd likely need a specialized filesystem that reorders requests > so that blocks are pulled from as many chips as possible at once for > maximum throughput. It would also have to handle block remapping, garbage > collection, etc. We'd just put an accessible ROM on there that lays out > the structure for the kernel driver.
How about this: PCI-E form factor board, with: * 1 CX4 Infiniband/10gigE connector, wired to FPGA * x1, x2, x4 PCI-E gen1/gen2, wired to FPGA * DIMM-type sockets for removable flash chip modules It looks like the Xilinx XC6SLX75T can support 8 GTP transceivers, that looks like it *might* support both the Infiniband and x4 PCI-E at the same time. (unless you need a 2 GTP's for a tx/rx pair) Are there other FPGA's that would work for this? (As for why infiniband, see http://seniord.ece.iastate.edu/may0904/ ) Let me add a crazy thought... Can we make GDDR5 'DIMMS' that could be put in instead of flash chip dimms, and throw on a displayport connector on the same board? (I probably just added $1500 to the cost for this craziness) _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
