On Sat, Mar 23, 2013 at 12:13 AM, <[email protected]> wrote:

> Le 2013-03-23 00:13, Timothy Normand Miller a écrit :
>
>> http://www.cs.binghamton.edu/~**millerti/ins-formats2.pdf<http://www.cs.binghamton.edu/~millerti/ins-formats2.pdf>
>>
>
> I would advise adding a ANDN instruction : AND with one inverted operand.
> it speeds up boolean MUX sequences for example.
>
> circuit-wise, there's a little trick :
> the "N" is done with the same circuit as the SUB,
> because you have to complement every bit of one operand
> in each case. So you have a parallelism between ADD/SUB
> and AND/ANDN.
>

You mean like how this is done with SSE, where we make masks and AND and OR
vectors together?  Yeah.  The thing is, since this is not a vector machine,
can we accomplish the same thing with the same or better performance using
conditional MOV?


>
>
> I also think that the WR flag should be infered from the opcode.
>

Yeah, so the three places are the opcode, the dest register (i.e. zero), or
an explicit bit.  I'm still letting my subconscious work on that, but I'm
starting to really like the idea of having a 31-bit immediate.  The
question is:  Which register do we store it in?  If we use R0 as a
bitbucket, then we can't use that; if we use the opcode then we can.  R31
is often used (by convention) for subroutine return address.  How do we
inform a compiler of the fact that this is special-purpose?  They have had
to deal with the fact that x86 has special-purpose registers, like how CX
is used for iteration count implicitly for some instructions, so probably
not a big deal.


>
> Otherwise, well, nice job :-)
>

Thanks.  :)


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-- 
Timothy Normand Miller, PhD
Assistant Professor of Computer Science, Binghamton University
http://www.cs.binghamton.edu/~millerti/
Open Graphics Project
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