On Sun, Mar 24, 2013 at 4:12 PM, Nicolas Boulay <[email protected]> wrote:
> Have you think to use a mix 32/64 bits instructions world ? You will offer > a true 32 bits immediat. > Any kind of variable length instructions would have more cost than benefit. > > You could also easly fit all instructions with 3 registers read and a > single write. The goal is to use 2 alus or a 3 inputs alu, without having > classical register dependancies. Modern cpu with large superscalar pipeline > have a little bit more than 2 instructions in average executed in > parrallel. So 2 instructions in parrallel could be reached. > Yeah, but since what we're designing a SIMT GPU, we'll get more throughput/area from scalar in-order multithreaded cores. > > A little bit larger instruction world permit to code in a single > instruction, what could be coded in 2 or 3 classical risc instruction > without the read dependancies of the registers, so the minimum latency will > be much lower. > You're talking about VLIW. The problem with VLIW is that it's a major challenge to keep all the instruction slots full. We'll have much higher code density AND throughput from a more traditional RISC ISA. > > Regards, > Nicolas > > 2013/3/24 Timothy Normand Miller <[email protected]> > >> Here's another version. >> http://www.cs.binghamton.edu/~millerti/ins-formats3.pdf >> >> * This time, I've gotten rid of the WR bit and made R0 the bitbucket. >> * The top bit of the instruction is 1 for an LL instruction that loads a >> 31-bit immediate into R1. For all others, it's 0. >> * I added some more RX type instructions that may be convenient, like >> FABS, and NOT. >> * FNEG is really just FSUB(R0,x) >> * I'd like to group the RX type instructions together, so maybe they >> should be renumbered, and I realized that, well, there are unused bits, so >> I could group all RX types into a single function type and then have a >> function2 field for more of those. But I'll put that off until we decide >> that the RR function space is crowded. >> * I just realized that we can now ditch the MOV instruction altogether >> and replace it with OR(R0,X), but I didn't make that change yet. >> * I renamed the R1 instruction type to RX to avoid confusion with the >> register R1. >> >> -- >> Timothy Normand Miller, PhD >> Assistant Professor of Computer Science, Binghamton University >> http://www.cs.binghamton.edu/~millerti/ >> Open Graphics Project >> >> _______________________________________________ >> Open-graphics mailing list >> [email protected] >> http://lists.duskglow.com/mailman/listinfo/open-graphics >> List service provided by Duskglow Consulting, LLC (www.duskglow.com) >> > > -- Timothy Normand Miller, PhD Assistant Professor of Computer Science, Binghamton University http://www.cs.binghamton.edu/~millerti/ Open Graphics Project
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