On Sat, Aug 09, 2014 at 04:04:29PM +0200, [email protected] wrote: > Le 2014-08-09 14:09, [email protected] a écrit : > >Le 2014-08-09 03:10, Troy Benjegerdes a écrit : > >>I have not looked far enough into lowRISC to see if it's actually > >>endian-sane. > > "The base ISA has been defined to have a little-endian memory > system, with big-endian or > bi-endian as non-standard variants." > > >I'll have to look closely at the ISA, I wonder how much or RISC-V was > >copied from MIPS... > > I see that David Patterson is on board so it should be pretty clean, > being the > 5th generation of Berkeley RISC designs... > > Note that it is an "open" specification but not "free" : > "We cannot guarantee that all RISC-V implementations will be free of > third-party patent > infringements, but we can guarantee we will not attempt to sue a > RISC-V implementor." > Thanks guys for being clear and honest about it :-D > > But as soon as I found the description of the variable-size > instruction encoding, > I stopped reading. It's KISS gone wrong...
I cannot for the life of me imagine why we'd need more than 42 bits for instruction encoding, 10 bits for instructions, and 32 bits for indexes/loads/etc. If we are really talking about new innovative architectures, why the hell are we stuck on powers-of-2? But, regardless, it will be nice to have OpenRISC and RISC-V to compare to Sparc V8 (already GPL and flying in Aerospace applications from Gaisler research.. http://www.gaisler.com/index.php/products/processors/leon3 ) Now if I could only get IBM to license PowerPC under the IBM public license.. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
