This release implements a simple shader cpu with related compiler, assembler, instruction level simulator/debugger, and (rough) rtl simulation framework. The shader cpu is Harvard architecture with closely associated small instruction and data BRAM memories. The shader cpu interacts with the framebuffer through a four entry scatter-gather dma unit. The shader core is presently integer only, though I have implemented floating point support using a custom assembly language library that the compiler silently calls when emitting floating point code.
In this release only a single shader cpu is instantiated by the rtl, and it is directly controlled by the host; a method extremely useful for testing, but not appropriate for future releases. This shader cpu allows processing graphics within the TVC at the level of small pre-transform bundles of triangles (16), instead of at the scanline level of previous releases. The shader language is c-like (should be like+=lots;) and the achieved objective was to be able to compile (with g++) and execute mostly unmodified shader programs in a framework on a development host to assist in shader program development. The developed compiler, written in C++, is completely un-optimizing, but as a result the generated assembly is quite readable (good for debugging). A simple keyhole optimization pass (or two) should significantly improve its output. This release was built using a Digilent Inc. Nexys(TM) 2 FPGA development board. This board has a Xilinx Spartan XC3S1200E FPGA and a 16MB micron PSRAM that I am using in synchronous mode at 80MHz for 160MB/sec theoretical peak memory bandwidth. The VGA output is 8 bit color via an on-board resistor network. For command input I use the USB-2.0 port on-board the Nexus2. This USB port is interfaced to the command bus implemented in release #4. The shader core is operating at 80MHz. The vast majority of this work has been done over the past 2.5 months. As a result of the compressed schedule there are plenty of bugs, in particular, known bugs in the compiler. Note: I am not releasing this entirely into the public domain as I have done in previous releases. I am not sure what license each component should be released under. Regardless, I've decided to release what I have built and sample the response. In this release I have maintained the core TVC elements (less the shader processor) in the Public Domain. For now see each file or directory for the applicable license. For future releases I am leaning toward either straight BSD or a mix of (L)GPL for the compiler, assembler, and simulator, and HDL released under either BSD or Public Domain (or a mix). See http://www.johnculp.net/TVC/ for more information. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
