Nicholas A. Sinnott-Armstrong wrote:
--- James Richard Tyrer wrote:
So, I was working on this since there are other ways to do this. I was
working on linear interpolation since this can be easily done with a
FPGA using the Bresenham Line-Drawing Algorithm. Even some overlap with
the graphics project.
---
I am a little confused about this -- how are we going to linear interpolate 1
bit?
No, we are starting with 24bit PCM. If you look at this SVGZ file:
http://home.earthlink.net/~tyrerj/files/OG/pcm2pwm-03A.svgz
the red lines show the possible liner interpolation of the PCM signal.
Is this method that you are proposing just filtering between bits of the PWM?
The idea is to smoothly transition to different pulse lengths in the
oversampling
instead of switching all of a sudden half an input sample in? That should be
quite
straightforward to implement in an FPGA.
Yes, you could probably use this for sample rate conversion too.
Although the usual sample rate conversion is from 44.1Ks/s to 48Ks/s.
Or, you could simply use the linear interpolation instead of sample rate
conversion.
---
One slight problem. Despite the fact that this paper was presented at
the AES convention, it is bunk.
See his diagrams on page 3. Notice that there are 4 samples for each 2
cycles of the of the triangle wave for the pulse width modulator. So
what happens is that the first pulse area is an average of the first 2
samples and the second pulse area is an average of the second two samples.
So, at 1/2 the sample rate, there is distortion, but this doesn't matter
since it is beyond 1/2 the frequency of the PWM. ARGH!
---
Doesn't _any_ digital (PWM) system introduce distortion of the analog signal?
Yes, but it is all supposed to be above 1/2 the sample rate.
---
The PWM output from the digital samples doesn't have to match the PWM
output that would have resulted from analog input. The Nyquist sampling
theory addresses that. The nice thing is that with audio we all have a
built in brick wall filter -- we can't hear stuff above 20KHz so it
doesn't matter.
---
Ok, that works. Stick a LPF in just to be safe ;-)
Yes, a class D amp has a filter, but it is really to eliminate RFI and
to protect the speakers.
---
So, this idea is useless. Yet it is true that your 192Ks/s audio is
going to be played on a class D amp with 44.1KHz | 48KHz PWM.
So, we do have the question of how much of this information is needed
and how to transform it into a PWM signal. Remember that you have a
3,221,225,472,000Hz bit rate. Yes, that is over 3 TERA Hz.
---
So this 3Tz comes from the quantization to 24 bits, and the fact that you
can just oversample the PWM to that frequency and reproduce every bit
perfectly?
It is the clock rate that is needed to perfectly convert a 24 bit
192Ks/s PCM signal into a PWM (1 bit) signal with no loss of
information. Actually you can cut this in half by using 23 bit and
separating the sign bit, but it is still too fast to be practical.
---
I don't think that you are going to be able to directly translate this into a
PWM signal. :-D A digital Bessel filter would probably be appropriate
so that you would simply loose much of the information over 48KHz. You
can't use an analog shelf to correct the response at 20KHz to 0dB so you
need another pole and zero in the digital filter). The problem comes
with the 24 bits. 2^23 is 8,388,608. It is simply not possible to run
the digital PWM at over 400 GHZ. So, this is an unsolved problem of HiFi.
---
The 400 Ghz from 48Khz instead of 192Ks/s for the perfect reproduction
PWM, right?
Yes, and still too fast for a chip to do directly. IIRC, even the ECL
Cray computers weren't that fast.
The problem looking for a solution is that, currently, to use the full
dynamic range of 24 bits, you have to use a DAC and then you have lost
some of the range anyway since analog doesn't have that kind of dynamic
range. From what I have read, many class D amps don't actually use the
full 15 bits (plus sign) from a CD, but rather throw part of them away
and then use noise shaping to mask this. I see claims of ICs that do
better but no explanation of how they work. E.G:
http://www.cirrus.com/en/pubs/proDatasheet/CS44600_F1.pdf
Another possibility is that it might be possible to use delay lines
rather than a fast clock to do this. The Xilinx chip has DCMs rather
than PLLs and I don't fully understand how they work except they use
delay lines.
--
JRT
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