--- James Richard Tyrer wrote: No, we are starting with 24bit PCM. If you look at this SVGZ file:
http://home.earthlink.net/~tyrerj/files/OG/pcm2pwm-03A.svgz the red lines show the possible liner interpolation of the PCM signal. --- OK, that makes more sense. --- continue quote --- > Doesn't _any_ digital (PWM) system introduce distortion of the analog signal? > Yes, but it is all supposed to be above 1/2 the sample rate. --- I understand that we can't just oversample more to reduce noise, but why doesn't the noise-shaping trick of sigma-delta ADCs (integrator) work here? We can just use a wide BPF, or even use the aforementioned brick wall filter our ears have (if the frequency is high enough, which it should be with 192Khz audio). --- continue quote --- Another possibility is that it might be possible to use delay lines rather than a fast clock to do this. The Xilinx chip has DCMs rather than PLLs and I don't fully understand how they work except they use delay lines. --- end of quote --- I have always been afraid of using delay lines and such to increase the apparent frequency, and this is especially true now that OGP has had issues with producing correct video waveforms using those DCMs. Delay lines could work with linear interpolation, however. It is not critical to get exactly the right values when doing the interpolation (since the level gets reset every clock cycle anyways), so they could lead to a high performance, reasonably accurate system. _______________________________________________ Open-hardware mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-hardware
