Could a gatekeeper review the attached patch to files
osprey/be/opt/opt_main.cxx and opt_cfg.[cxx,h]? Here is the
description:
When we enhanced the control flow optimization to handle the PU with
EH regions in the previous release, we added a region exit block for
each EH region during the CFG construction. These extra blocks are
unnecessary when CFG is built but no control flow optimization is
performed. Indeed, control flow optimization only happens in mainopt.
These unnecessary extra blocks may cause "out of memory" issue in
preopt. Thus, this change is to add these region exit blocks only when
CFG control flow optimization is performed (i.e. mainopt).
Thanks,
-David Coakley / AMD Open Source Compiler Engineering
Index: osprey/be/opt/opt_cfg.h
===================================================================
--- osprey/be/opt/opt_cfg.h (revision 3681)
+++ osprey/be/opt/opt_cfg.h (working copy)
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (C) 2008-2011 Advanced Micro Devices, Inc. All Rights Reserved.
*/
//-*-c++-*-
@@ -241,6 +241,9 @@
BB_NODE_SET *_bb_set; // A scratch bb set for temporary use
BB_NODE_SET *_non_true_body_set; // scratch bb set for use in Compute_true_loop_body_set
+ BOOL _cfg_transform; // we don't need to add extra data struct to cfg if
+ // CFG_transformation will not be performed
+
CFG(const CFG&);
CFG(void);
CFG& operator = (const CFG&);
@@ -470,7 +473,8 @@
// preopt/mainopt/rvi
OPT_STAB *opt_stab,// optimizer symbol table
BOOL do_tail, // do tail recursion?
- MEM_POOL * sc_pool); // pool for SC nodes and trees
+ MEM_POOL * sc_pool, // pool for SC nodes and trees
+ BOOL cfg_transform = FALSE);
void Compute_dom_tree // compute dominator tree or
(BOOL build_dom); // post-dominator tree
Index: osprey/be/opt/opt_main.cxx
===================================================================
--- osprey/be/opt/opt_main.cxx (revision 3681)
+++ osprey/be/opt/opt_main.cxx (working copy)
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (C) 2008-2011 Advanced Micro Devices, Inc. All Rights Reserved.
*/
//-*-c++-*-
@@ -1508,7 +1508,7 @@
WOPT_Enable_Calls_Break_BB,
rgn_level/*context*/,
comp_unit->Opt_stab(), do_tail_rec,
- Malloc_Mem_Pool);
+ Malloc_Mem_Pool, phase == MAINOPT_PHASE);
// Transfer feedback data from Whirl annotation (at Cur_PU_Feedback)
// to optimizer CFG annotation (at comp_unit->Cfg()->Feedback())
Index: osprey/be/opt/opt_cfg.cxx
===================================================================
--- osprey/be/opt/opt_cfg.cxx (revision 3681)
+++ osprey/be/opt/opt_cfg.cxx (working copy)
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2008-2010 Advanced Micro Devices, Inc. All Rights Reserved.
+ * Copyright (C) 2008-2011 Advanced Micro Devices, Inc. All Rights Reserved.
*/
/*
@@ -2698,7 +2698,9 @@
}
#endif
- if (REGION_is_EH(wn))
+ // if we are not doing cfg_transformation, we don't need to add
+ // regionexit block, which is only used when we do cfg_transformation
+ if (_cfg_transform && REGION_is_EH(wn))
{
if (_current_bb->Succ() ||
_current_bb->Kind() == BB_EXIT)
@@ -3849,13 +3851,15 @@
void
CFG::Create(WN *func_wn, BOOL lower_fully, BOOL calls_break,
- REGION_LEVEL rgn_level, OPT_STAB *opt_stab, BOOL do_tail, MEM_POOL * sc_pool )
+ REGION_LEVEL rgn_level, OPT_STAB *opt_stab, BOOL do_tail, MEM_POOL * sc_pool,
+ BOOL cfg_transform)
{
_opt_stab = opt_stab;
_lower_fully = lower_fully;
_calls_break = calls_break;
_rgn_level = rgn_level; // context: preopt/mainopt/rvi
_sc_pool = sc_pool;
+ _cfg_transform = cfg_transform;
Set_cur_loop_depth( 0 );
@@ -3914,7 +3918,8 @@
opt_tail.Mutate();
}
- Ident_eh_regions();
+ if (_cfg_transform)
+ Ident_eh_regions();
Process_multi_entryexit( TRUE/*is_whirl*/ );
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