Author: rramanar
Date: 2011-09-06 04:57:48 -0400 (Tue, 06 Sep 2011)
New Revision: 3731
Modified:
trunk/osprey/be/cg/x8664/expand.cxx
trunk/osprey/be/com/wn_lower.cxx
trunk/osprey/wgen/wgen_expr.cxx
Log:
popcnt is now generated for call to builtin_popcnt on Barcelona
and above. I use the following check: Is_Target_SSE42() ||
Is_Target_Barcelona()
Is_Target_SSE42 enables it on Orochi. Is_Target_Barcelona enables it
on Barcelona.
Thanks to Jian-Xin Lai for code review.
Modified: trunk/osprey/be/cg/x8664/expand.cxx
===================================================================
--- trunk/osprey/be/cg/x8664/expand.cxx 2011-09-02 02:45:01 UTC (rev 3730)
+++ trunk/osprey/be/cg/x8664/expand.cxx 2011-09-06 08:57:48 UTC (rev 3731)
@@ -8856,8 +8856,8 @@
Build_OP(TOP_vmovaps, result, op0, ops );
break;
case INTRN_I2POPCNT:
- if ( Is_Target_SSE42() || Is_Target_SSE4a() ) {
- // SSE4.2(Intel) and SSE4a(AMD) supports popcnt
+ if ( Is_Target_SSE42() || Is_Target_Barcelona()) {
+ // popcnt available since Barcelona and Nehalem
Build_OP(TOP_popcnt16, result, op0, ops);
}
else {
@@ -8865,8 +8865,8 @@
}
break;
case INTRN_I4POPCNT:
- if ( Is_Target_SSE42() || Is_Target_SSE4a() ) {
- // SSE4.2(Intel) and SSE4a(AMD) supports popcnt
+ if ( Is_Target_SSE42() || Is_Target_Barcelona()) {
+ // popcnt available since Barcelona and Nehalem
Build_OP(TOP_popcnt32, result, op0, ops);
}
else {
@@ -8875,8 +8875,8 @@
break;
case INTRN_I8POPCNT:
if ( Is_Target_64bit() &&
- ( Is_Target_SSE42() || Is_Target_SSE4a() ) ) {
- // SSE4.2(Intel) and SSE4a(AMD) supports popcnt
+ ( Is_Target_SSE42() || Is_Target_Barcelona()) ) {
+ // popcnt available since Barcelona and Nehalem
Build_OP(TOP_popcnt64, result, op0, ops);
}
else {
Modified: trunk/osprey/be/com/wn_lower.cxx
===================================================================
--- trunk/osprey/be/com/wn_lower.cxx 2011-09-02 02:45:01 UTC (rev 3730)
+++ trunk/osprey/be/com/wn_lower.cxx 2011-09-06 08:57:48 UTC (rev 3731)
@@ -5911,13 +5911,16 @@
}
if( ( (INTRINSIC)WN_intrinsic(tree) == INTRN_I2POPCNT ||
(INTRINSIC)WN_intrinsic(tree) == INTRN_I4POPCNT ) &&
- ( Is_Target_SSE42() || Is_Target_SSE4a() ) ) {
- // SSE4.2(Intel) and SSE4a(AMD) supports I2 and I4 popcnt
+ ( Is_Target_SSE42() || Is_Target_Barcelona()
+ || Is_Target_Orochi()) ) {
+ // Support for POPCNT is available with AMD
+ // Barcelona onwards and Intel Nehalem onwards
break;
}
if( (INTRINSIC)WN_intrinsic(tree) == INTRN_I8POPCNT &&
- Is_Target_64bit() && ( Is_Target_SSE42() || Is_Target_SSE4a() ) ) {
- // SSE4.2(Intel) and SSE4a(AMD) supports I8 popcnt in 64-bit mode
+ Is_Target_64bit() && ( Is_Target_SSE42() || Is_Target_Barcelona() ) ) {
+ // Support for POPCNT is available with AMD
+ // Barcelona onwards and Intel Nehalem onwards
break;
}
#endif
Modified: trunk/osprey/wgen/wgen_expr.cxx
===================================================================
--- trunk/osprey/wgen/wgen_expr.cxx 2011-09-02 02:45:01 UTC (rev 3730)
+++ trunk/osprey/wgen/wgen_expr.cxx 2011-09-06 08:57:48 UTC (rev 3731)
@@ -9200,12 +9200,27 @@
intrinsic_op = TRUE;
break;
+#ifdef TARG_X8664
case GSBI_BUILT_IN_POPCOUNT:
+ iopc = INTRN_I4POPCNT;
+ intrinsic_op = TRUE;
+ break;
case GSBI_BUILT_IN_POPCOUNTL:
+ iopc = INTRN_I8POPCNT;
+ intrinsic_op = TRUE;
+ break;
case GSBI_BUILT_IN_POPCOUNTLL:
iopc = INTRN_POPCOUNT;
intrinsic_op = TRUE;
break;
+#else
+ case GSBI_BUILT_IN_POPCOUNT:
+ case GSBI_BUILT_IN_POPCOUNTL:
+ case GSBI_BUILT_IN_POPCOUNTLL:
+ iopc = INTRN_POPCOUNT;
+ intrinsic_op = TRUE;
+ break;
+#endif
case GSBI_BUILT_IN_PARITY:
case GSBI_BUILT_IN_PARITYL:
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